CVE-2025-0647_CVE-2025-0647

5.4 / 10

MEDIUM

CVSS:3.1/AV:N/AC:L/PR:L/UI:N/S:U/C:L/I:L/A:N

Description

In certain Arm CPUs, a CPP RCTX instruction executed on one Processing Element (PE) may inhibit TLB invalidation when a TLBI is issued to the PE, either by the same PE or another PE in the shareability domain. In this case, the PE may retain stale TLB entries which should have been invalidated by the TLBI.

Basic Information

ID CVE-2025-0647

Source Arm

Published Jan 14, 2026 at 10:58

Modified Jan 15, 2026 at 20:46

Affected Product

Vendor Arm

Product Neoverse-N2

Affected Versions Arm Neoverse-N2 0
Arm Neoverse-V3AE 0
Arm Neoverse-V3 0
Arm Neoverse-V2 0
Arm Cortex-X925 0
Arm Cortex-X4 0
Arm Cortex-X3 0
Arm Cortex-X2 0
Arm Cortex-A710 0
Arm C1-Premium 0
Arm C1-Ultra 0

CWE Classification

CWE-226

References

developer.arm.com /documentation/111546

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    "published": "2026-01-14T10:58:44.342Z",
    "modified": "2026-01-15T20:46:07.810Z",
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